1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to SOI semiconductor devices comprising semiconductor elements, such as substrate diodes, that are formed in the crystalline material of the substrate.
2. Description of the Related Art
The fabrication of integrated circuits requires a large number of circuit elements, such as transistors and the like, to be formed on a given chip area according to a specified circuit layout. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips, ASICs (application specific ICs) and the like, CMOS technology is one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed above a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the distance between the source and drain regions, which is also referred to as channel length. Therefore, reducing the feature sizes and, in particular, the gate length of the field effect transistors has been an important design criterion.
In view of further enhancing performance of transistors, in addition to other advantages, the SOI (semiconductor- or silicon-on-insulator) architecture has been continuously gaining in importance for manufacturing MOS transistors due to their characteristics of a reduced parasitic capacitance of the PN junctions, thereby allowing higher switching speeds compared to bulk transistors. In SOI transistors, the semiconductor region, in which the drain and source regions as well as the channel region are located, also referred to as the body, is dielectrically encapsulated. This configuration provides significant advantages, but also gives rise to a plurality of issues.
For example, semiconductor elements, such as diodes and the like, may have to be implemented in the substrate material due to certain device requirements, thereby necessitating the formation of appropriate areas in which the substrate material has to be exposed. Any such area may be referred to as a substrate window and may affect the further processing due to a pronounced surface topography. For example, one important issue in high performance devices, such as microprocessors and the like, is an efficient device internal temperature management due to the significant heat generation of the transistors. Due to the reduced heat dissipation capability of SOI devices caused by the buried insulating layer, the corresponding sensing of the momentary temperature in SOI devices is of particular importance. Typically, for thermal sensing applications, an appropriate diode structure may be used wherein the characteristic of the diode may permit information to be obtained on the thermal conditions in the vicinity of the diode structure. The sensitivity and the accuracy of the respective measurement data obtained on the basis of the diode structure may significantly depend on the diode characteristic, i.e., on the diode's current/voltage characteristic, which may depend on temperature and other parameters. For thermal sensing applications, it may, therefore, typically be desirable to provide a substantially “ideal” diode characteristic in order to allow a precise estimation of the temperature conditions within the semiconductor device. In SOI devices, a corresponding diode structure, i.e., the respective PN junction, is frequently formed in a substrate window area, i.e., in the substrate material located below the buried insulating layer, above which is formed the “active” semiconductor layer used for forming therein the transistor elements. Thus, at least some additional process steps may be required, for instance, for etching through the semiconductor layer or a corresponding trench isolation area and through the buried insulating layer in order to expose the crystalline substrate material. On the other hand, the process flow for forming the substrate diode is typically designed so as to exhibit a high degree of compatibility with the process sequence for forming the actual circuit elements, such as the transistor structures.
Although providing substrate diodes in sophisticated SOI semiconductor devices is a promising approach for obtaining reliable temperature data during the operation of the semiconductor device, conventional approaches for forming substrate diodes may result in significant yield losses and, thus, loss of performance in the corresponding substrate window due to the continuous shrinkage of device features, such as transistors, lines and the like. For example, in sophisticated semiconductor devices comprising field effect transistors, the gate length has reached values of approximately 40 nm and less, thereby increasing packing density and also providing superior performance of the individual transistors. Similarly, the wiring network, i.e., the metallization system in combination with an appropriate contact level, has to be appropriately adapted to the increased packing density in the device level of sophisticated semiconductor devices, thereby also requiring contact elements and metal features of reduced lateral dimensions. At the same time, the thickness or height of the various metallization levels may have to be reduced so as to correspond to the reduced lateral dimensions. During the fabrication of contact levels, i.e., the dielectric material and the corresponding contact elements formed therein that connect to the contact areas of the semiconductor-based circuit elements, and during the fabrication of the metallization layers of the complex metallization system, a plurality of very complex processes, such as lithography processes, deposition and patterning processes, have to be applied, which may be very sensitive to the overall surface topography of the semiconductor device at a specific manufacturing stage under consideration. In particular, any material removal processes based on a polishing process have been identified to cause significant irregularities when forming contact elements and metallization layers, as will be described in more detail with reference to FIG. 1.
FIG. 1 schematically illustrates a cross-sectional view of a semiconductor device 100, which represents an SOI device, since the device 100 comprises a substrate 101, a buried insulating layer 103 and a silicon-based semiconductor layer 104. The substrate 101 may represent a silicon substrate and, thus, comprises a crystalline substrate material 102, above which is formed the buried insulating layer 103, which is typically comprised of silicon dioxide. As illustrated, in a certain device area 110A the buried insulating material 103 and the semiconductor layer 104 are at least partially removed in order to provide any circuit elements in the device area 110A within the crystalline substrate material 102. As previously indicated, the device area 110A may also be referred to as a substrate window and is frequently used for implementing a plurality of substrate diodes 150 in and above the crystalline substrate material 202 within the device area 110A. On the other hand, a device area 110B comprises the semiconductor layer 104, in and above which circuit elements are formed, such as sophisticated transistors and the like, wherein, for convenience, a single transistor element 160 is illustrated in FIG. 1.
As discussed above, in sophisticated applications, the transistor 160 may comprise a gate electrode structure 161 having a gate length of approximately 40 nm and less. Furthermore, the transistor 160 comprises drain and source regions 162, wherein at least deeper areas thereof have substantially the same configuration, i.e., dopant concentration, as highly doped regions 152 of the substrate diode 150, wherein, however, the doped regions 152 are formed within an appropriately doped well region 102W provided in the crystalline substrate material 102 within the device area 110A. Similarly, the substrate diodes 150 may further comprise highly doped areas 153, which have a similar configuration as any drain and source regions of transistor elements of inverse conductivity type compared to the transistor 160. For convenience, any such transistors are not illustrated in FIG. 1. In the example shown, the transistor 160 may represent an N-channel transistor and, thus, the drain and source regions 162 and the highly doped regions 152 represent N-doped regions. In combination with an N-type doping in the well region 102W, the regions 152 may represent the cathode of the substrate diodes 150. On the other hand, the P-doped regions 153 may form a PN junction 102P with the N-type well region 102W and may, thus, act as anodes of the substrate diodes 150. Moreover, as illustrated, in view of reducing contact resistivity of the circuit elements 160 and 150, metal silicide regions 164 and 151, respectively, may be provided in the highly doped regions 162, 152, 153, for instance in the form of nickel silicide and the like. The cathode side, i.e., the region 152, and the anode side, i.e., the region 153, in each substrate diode 150 are separated by a portion of the well region 102W above which portions of the buried insulating layer 103 and the semiconductor layer 104 are provided, as indicated as 103D, 104D. Depending on the overall process strategy, additional materials, such as a gate dielectric material, an electrode material, such as polysilicon, and the like, may be formed above the portions 104D. It should further be appreciated that, in other cases, the portions 104D may represent an insulating material, i.e., the residues of isolation structures that are typically formed in the semiconductor layer 104 in order to laterally delineate corresponding active regions or semiconductor regions, in and above which are formed circuit elements, such as the transistor 160 and the like. For convenience, any such isolation structures are not shown in FIG. 1. Above the device level, i.e., the semiconductor layer 104 and any circuit elements formed therein and thereabove, such as the transistor 160, and above the substrate diodes 150 within the device area 110A, a contact level 120 is provided, which may be considered as an interface for connecting the circuit elements 160, 150 with a metallization system, of which a very first metallization layer 130 is illustrated, for convenience. The contact level 120 comprises one or more appropriate dielectric materials, such as a layer 121 in combination with a layer 122 provided, for instance, in the form of silicon nitride and silicon dioxide, respectively. Additionally, the contact level 120 comprises contact elements 123A, 123B that connect to the doped semiconductor regions 152, 153 on the one hand and to doped semiconductor regions in the layer 104, such as the drain and source regions 162, on the other hand. The contact elements 123A, 123B are provided in the form of any appropriate conductive material, such as tungsten, aluminum and the like, possibly in combination with appropriate conductive barrier materials, such as titanium nitride, titanium and the like.
The metallization layer 130 comprises any appropriate dielectric material or materials, such as low-k dielectric materials, which are to be understood as dielectric materials having a dielectric constant of 3.0 and less, in combination with any other materials, such as etch stop layers (not shown) and the like. Furthermore, metal lines 133A are provided in the dielectric material 131 so as to connect to the contact elements 123A within the device area 110A, while metal lines 133B connect to the contact elements 123B in the device area 110B. The metal lines 133A, 133B are typically comprised of copper in combination with appropriate conductive barrier materials, such as tantalum, tantalum nitride and the like.
The semiconductor device 100 as illustrate in FIG. 1 may be formed on the basis of the following process strategy. The well region 102W of the crystalline substrate material 102 within the device area 110A may be formed at any appropriate manufacturing stage, i.e., upon forming corresponding active regions in the semiconductor layer 104 by performing masked implantation processes. To this end, a high energy implantation process is performed to implant the well dopant species of the region 102W through the layers 104 and 103 and into the crystalline substrate material 102. In other cases, the substrate window 110A may be formed first by providing an appropriate etch mask so as to etch through the layers 104, 103, thereby exposing portions of the substrate material 102 within the device area 110A, while preserving the portions 104D, 103D. In other cases, a corresponding etch process for exposing portions of the material 102 within the area 110A may be performed after forming corresponding gate electrode structures, such as the gate electrode structure 161 of the transistor 160. Thereafter, any appropriate processes are performed so as to complete the transistor 160, thereby performing appropriate implantation processes for forming the drain and source regions 162 of N-type and P-type transistors, thereby also applying an appropriate masking regime for forming the highly doped regions 152 and 153 of the substrate diodes 150. After any anneal processes for activating dopants and re-crystallizing implantation-induced damage, while also initiating a dopant diffusion, if desired, the metal silicide regions 164, 151 may be commonly formed in the transistor 160 and the substrate diodes 150. Consequently, the circuit elements 160 and 150 may be formed on the basis of substantially the same process sequence, thereby providing a very efficient overall manufacturing flow, while, however, a significant difference in height level between the device area 110A and 110B is generated. The pronounced surface topography caused by this difference in height levels, in turn, may result in significant irregularities in the further processing of the device 100. That is, upon depositing the dielectric material or materials of the contact level, a certain degree of height difference may still exist between the device areas 110A, 110B. That is, typically, the material 121, such as a silicon nitride material, is deposited on the basis of plasma enhanced chemical vapor deposition (CVD) techniques having a more or less conformal deposition behavior. Thereafter, the material 122, for instance in the form of silicon dioxide, is deposited, for instance, by a deposition technique of superior gap filling capability, for instance high density plasma CVD, sub-atmospheric CVD, thereby providing a certain degree of leveling between the areas 110A, 110B, wherein, however, a certain global difference in height level may still exist, even if performing any additional polishing processes for improving the overall surface topography. After providing the dielectric material 122, sophisticated lithography processes are applied in order to form an appropriate etch mask, for instance in the form of a hard mask, a resist mask and the like, which may be used during the subsequent anisotropic etch sequence for etching through the material 122 and finally through the material 121 and into the metal silicide regions 164, 151. Thereafter, the contact openings are filled with the desired conductive material, possibly in combination with a conductive barrier material, and any excess material thereof is removed by chemical mechanical polishing (CMP), wherein process parameters have to be adapted so as to also reliably remove any metal residues in the device area 110A having the reduced global height level. In device generations including transistor elements of approximately 60 nm gate length, a corresponding difference in height level, as indicated by 110H, has been taken into consideration by providing the dielectric material 122 with increased thickness so as to generally take advantage of the non-conformal deposition behavior, possibly in combination with the leveling effect of a CMP process, while the removal of any excess material of the contact elements 123A, 123B has been performed on the basis of process parameters in which a high degree of “dishing” is achieved, i.e., a superior removal of metal compared to the dielectric material 122. In this manner, the excess metal of the contact level may be removed efficiently from within the device area 110A, which, however, may result in a height level difference 110H of approximately 60 nm and even more. Thereafter, the metallization layer 130 is formed by depositing the dielectric material 131 based on any appropriate process strategy, followed by the patterning of the material 131 based on sophisticated lithography techniques. Next, any appropriate conductive barrier material (not shown) is deposited, followed by the deposition of the actual fill material, such as copper and the like. Thereafter, any excess material is removed by appropriate planarization techniques, such as CMP, thereby also requiring the removal of the conductive materials within the device area 110A, which may have a different height level (110D). Consequently, upon reliably removing any metal residues from within the device area 110A, a significant reduction in thickness of the metallization layer 130 in the device area 110B may result, which may, thus, reduce performance of any metal lines 133B provided therein.
Upon further scaling the size of the individual circuit elements, lateral feature sizes and generally the thickness of the metallization layer 130 also has to be adapted. For example, in technologies using a gate length of 40 nm and less, a thickness of the metallization layer 130 may be of a similar order of magnitude as the height differences 110H or 110D, which would, thus, lead to a non-acceptable reduced thickness of the metallization layer 130 in the device area 110B after having reliably removed the excess material in the device area 110A. On the other hand, further increasing the thickness of the dielectric material 122 of the contact level 120 so as to further reduce the height difference 110H may not be a promising option, since significant variations may occur during the complex patterning process for forming the contact elements 123A, 123B due to, for instance, the significant height differences at a generally increased etch depth in the contact level, thereby contributing to significant substrate-to-substrate variations. Consequently, in the conventional approach, typically, a compromise of CMP parameters and thickness of the levels 120 and 130 may be applied, while, however, a significant probability exists that any metal residues may remain in the device area 110A after completing the corresponding polishing process. In this case, leakage paths or short circuits between metal lines 133A may be created, thereby at least reducing performance of the substrate diodes 150 or causing a complete failure of one of these devices. Since reliable temperature data may strongly depend on the diode characteristics, a reduction in the reliability or a degradation of performance of the substrate diodes may contribute to significant yield losses and/or reduced functionality of the semiconductor device 100.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.